The ADCP9268-80/105/125 is a dual-channel, 16-bit, 80/105/125MSPS analog-to-digital converter (ADC) powered by a 1.8V supply. It features integrated high-performance sample-and-hold circuitry and an on-chip reference voltage source. Employing a multi-stage differential pipelined architecture with built-in output error correction logic, it provides 16 -bit accuracy at a 125MSPS data rate and guarantees no missing codes across the entire operating temperature range. This ADC incorporates various features to optimize device flexibility and minimize system cost, such as generating programmable digital test codes.

Available digital test codes include built-in fixed codes and pseudo-random codes, as well as user-defined test codes input via a serial port interface (SPI) . A single differential clock input controls all internal conversion cycles. The digital output data format is offset binary, Gray code, or two's complement. Each ADC channel has a data output clock (DCO) to ensure correct latching timing for the receive logic. This device supports 1.8V CMOS output and LVDS output, and the output data can be multiplexed on a single output bus. It uses a RoHS- compliant 64-pin QFN.

• Low power consumption : 495mW (125MSPS).
• 1.8V analog power supply.
• 1.8V CMOS or LVDS output power supply.
• Signal-to-noise ratio (SNR) = 76.6 dBFS (Fin=30.5MHz@125MSPS).
• Spurious-free dynamic range (SFDR) = 88 dBc (Fin=30.5MHz@125MSPS).
• On-chip reference voltage source and sample-and-hold circuit.
• QFN-64 package , 9mm x 9mm.

• Communication.
• Diversity radio system.
• Multi-mode digital receiver (3G).
• I/O demodulation system.
• Smart antenna system.
• Battery-powered meters.
• Battery-powered meters.
• Portable medical imaging.
• Ultrasonic equipment.
• Radar /LIDAR.